Testing Digital Circuits with Constraints

* This work was done at Stanford-CRC and was supported by King Fahd University of Petroleum and Minerals. It was also supported by DARPA under contract No. DABT63-97-C-0024 (ROAR project). The authors would like to thank Chien-Mo Li and Chao-Wen Tseng for their help. Abstract Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of logic values in digital circuits and two techniques for preventing them from damaging the circuit or corrupting the test results. The hardware overhead of our technique is minimal and imposes negligible delay overhead. Simulation results show that the area overhead of our techniques is less than 1%. Unlike previous techniques, the fault coverage of the legal test patterns in a given test set is not sacrificed with our techniques. Furthermore, our techniques are applicable during IC production test, BIST, board-level tests and system-level tests.